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| Title Details: | |
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Circuit design with VHDL language |
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| Authors: |
Leligkou, Eleni Ekaterini Voliotis, Stamatis Kakarountas, Athanasios |
| Reviewer: |
Assimakis, Nikolaos |
| Description: | |
| Technical Editors: |
Vourvoulakis, John Kokkinou, Evdoxia Kritou, Evmorfia |
| Type: |
Chapter |
| Creation Date: | 16-09-2016 |
| Item Details: | |
| License: |
Attribution – NonCommercial – NoDerivatives 4.0 International (CC BY-NC-ND 4.0) |
| Handle | http://hdl.handle.net/11419/6441 |
| Bibliographic Reference: | Leligkou, E., Voliotis, S., & Kakarountas, A. (2016). Circuit design with VHDL language [Chapter]. In Leligkou, E., Voliotis, S., & Kakarountas, A. 2016. Logic Design in the Laboratory [Laboratory Guide]. Kallipos, Open Academic Editions. https://hdl.handle.net/11419/6441 |
| Language: |
Greek |
| Is Part of: |
Logic Design in the Laboratory |
| Publication Origin: |
Kallipos, Open Academic Editions |