Title Details: | |
Laboratory Exercise: Development of quantized neural networks on a RISC-V processor in FPGA Nexys A7 |
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Authors: |
Dasygenis, Minas Soudris, Dimitrios |
Description: | |
Abstract: |
PYNQ is an abbreviation for Python programming implementation of ZYNQ. From a hardware architecture perspective, the PYNQ core chip is a ZYNQ FPGA SOC, which combines programmable logic with a programmable system to perform sampling, processing, and signal generation. The aim of the project is the implementation of a "Neural Network Language Model" on the PYNQ platform, Xilinx. Two main topics need to be developed in this project: (a) FPGA design with Python and (b) development of a Deep Neural Network model on a small embedded system. The content of the exercise includes the use of the PYNQ board, deep neural network design and network training, FPGA accelerator design, as well as Python programming on FPGA.
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Linguistic Editors: |
Kagiadaki, Sofia |
Technical Editors: |
Dasygenis, Minas |
Graphic Editors: |
Dasygenis, Minas |
Type: |
Chapter |
Creation Date: | 28-08-2024 |
Item Details: | |
License: |
Attribution - NonCommercial - ShareAlike 4.0 International (CC BY-NC-SA 4.0) |
Handle | http://hdl.handle.net/11419/13881 |
Bibliographic Reference: | Dasygenis, M., & Soudris, D. (2024). Laboratory Exercise: Development of quantized neural networks on a RISC-V processor in FPGA Nexys A7 [Chapter]. In Dasygenis, M., & Soudris, D. 2024. Internet of Things Computing [Undergraduate textbook]. Kallipos, Open Academic Editions. https://hdl.handle.net/11419/13881 |
Language: |
Greek |
Is Part of: |
Internet of Things Computing |
Publication Origin: |
Kallipos, Open Academic Editions |